1. Field of the Invention
The present invention is directed to image sensors and, more particularly, to systems for reading out the contents of pixels in image sensors.
2. Discussion of Related Art
Image sensors are used to generate images based upon the outputs of a large number of light-sensitive pixels. Pixels commonly are arranged in an area array of “n-by-m” pixels (an area sensor). Each pixel in such an array generates an output signal that is proportional to an amount of light that is incident on that pixel during a so-called “integration period.” All of the pixels in the array generally are permitted to “integrate” for a predetermined amount of time during an integration period and the contents of the pixels in the array are individually “read out” during a so-called “read out period.” In this manner, an image may be generated based upon the contents of the pixels in the array.
FIG. 1 shows an area array of pixels and a prior art system for reading out the contents of each pixel in the array. As shown, the array includes “n+1” rows and “m+1” columns of pixels. Only the pixels in the comers of the array are illustrated in FIG. 1. The first row of pixels (i.e., row “0”) includes pixels P0,0 through P0,m, and the final row of pixels (i.e., row “n”) includes pixels Pn,0 through Pn,m. Similarly, the first column of pixels (i.e., column “0”) includes pixels P0,0 through Pn,0, and the final column of pixels (i.e., column “m”) includes pixels P0,m through Pn,m.
Each column of pixels in FIG. 1 is associated with a column readout line (CRL), a correlated double-sampling (CDS) circuit, and a row-select switch (RSS). In the example shown, pixel column “0” is associated with column readout line CRL0, correlated double-sampling circuit CDS0 and column-select switch CSS0, and pixel column “m” is associated with column readout line CRLm, correlated double-sampling circuit CDSm and column-select switch CSSm. Each column-select switch is connected to a common array readout line ARL.
Each row of pixels in the FIG. 1 circuit has a group of row-select switches (RSSs) associated with it. Each group of row-select switches selectively connects the outputs of the pixels in a particular row to respective column readout lines. In the example shown, pixel row “0” includes row-select switches RSS0,0 through RSS0,m, which selectively connect the outputs of pixels P0,0 through P0,m, respectively, to column readout lines CRL[0 . . . m]. Similarly, pixel row “n” includes row-select switches RSSn,0 through RSSn,m, which selectively connect the outputs of pixels Pn,0 through Pn,m, respectively, to column readout lines CRL[0 . . . m].
Typically, all pixels in the array, i.e., pixels P0,0 through Pn,m, are simultaneously caused to integrated charge using signals on control lines (not shown). After an integration period, each of pixels P0,0 through Pn,m stores a charge that is proportional to the intensity of the light that was incident on it during the integration period. Commonly, circuitry in each of the pixels converts this charge into a voltage and this voltage is provided at the output of the pixel. Rows of pixels are selected one-at-a-time by sequentially closing one group of row-select switches at a time. For example, pixel row “0” may be selected by closing row-select switches RSS0,0 through RSS0,m to provide the contents of pixels P0,0 through P0,m, respectively, to column readout lines CRL[0 . . . m].
After a particular row of pixels has been selected, control signals cause each of correlated double-sampling circuits CDS[0 . . . m] to sample the voltages presented on column readout lines CRL[0 . . . m], respectively, by the pixels in the selected row. Correlated double-sampling circuits CDS[0 . . . m] operate simultaneously for each row. After the output voltages of a particular row of pixels has been sampled by correlated double-sampling circuits CDS[0 . . . m], each of the pixels in the selected row is reset to its non-integrated state. Correlated double-sampling circuits CDS[0 . . . m] then sample the voltages from the outputs of the selected row of pixels a second time. The configuration of correlated double-sampling circuits CDS[0 . . . m] during this second sampling period cause voltages equal to the differences between the first voltages sampled and the second voltages sampled to be provided at their outputs.
After both samples have been taken by correlated double-sampling circuits CDS[0 . . . m] column-select switches CSS[0 . . . m] are closed one at a time to permit external circuitry (not shown) to measure the amplitude of the voltage on array readout line ARL when each column-select switch is closed, to amplify this voltage, and to convert the voltage into a digital output signal.
Thus, row-select switches RSS0,0 through RSSn,m and correlated double-sampling circuits CDS[0 . . . m] sample the output voltages of one row of pixels at a time, and column-select switches CSS[0 . . . m] select the outputs of correlated sampling circuits CDS[0 . . . m] one at a time, thereby providing the output voltage of each of pixels P0,0 through Pn,m to array readout line ARL one at a time.
When each of column-select switches CSS[0 . . . m] is closed to provide the output of the corresponding correlated double-sampling circuit to array readout line ARL, a certain period of time is required to allow the signal on array readout line ARL to settle before using external circuitry to measure the voltage on the line. This settling time is determined primarily by the capacitance of array readout line ARL.
Column-select switches CSS[0 . . . m] generally are implemented using metal oxide semiconductor (MOS) transistors. Each of these MOS transistors has a gate-to-source or gate-to-drain capacitance associated with it that, when connected to array readout line ARL, incrementally increases the readout line's overall capacitance. An area array having a large number of columns requires a large number of column-select switches to selectively provide the outputs of the correlated double-sampling circuits to the readout line for the array. The capacitance added by each of these column-select switches to the total capacitance of array readout line ARL limits the rate at which the outputs of the correlated double-sampling circuits can be selected and therefore limits the rate at which the contents of the pixels in the array may be read out.
Similarly, because each of column-select switches CSS[0 . . . m] is connected to array readout line ARL via a circuit trace having a particular length, each such circuit trace incrementally increases the overall capacitance of array readout line ARL. The capacitance added by each of these circuit traces to the total capacitance of array readout line ARL also limits the rate at which the outputs of the correlated double-sampling circuit can be selected and therefore further limits the rate at which the contents of the pixels in the array may be read out.
What is needed, therefore, is an improved pixel readout scheme for image sensors.